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technical data 2012, january, ver.01 osci a0 gnd v cc int scl sd a 1 2 3 4 8 7 6 5 osco cmos timer with ram and i 2 c- bus control . ina8583n is a timer with ram and i 2 c - bus control. designed for use in appliances having i 2 c - bus as clock/ calendar/ timer/ alarm/ events counter for turning on functions of the a p pliance at preset time or upon completion of an event. to be used in a u dio and appliances. features: ? i 2 c - bus interface operating supply voltage: 2.5 v to 6 v ? clock operating supply voltage ( 0 70 ): 1.0 v to 6 v ? operating current (at f scl = 0hz): 50 ? clock function with four year calendar ? 24 or 12 hour format ? 32.768 khz or 50hz time base ? serial bus (i 2 c) ? automatic word address in crementation ? programmable a larm, timer and interrupt function ? operating temperature range: - 20 to +70 ordering infor mation table1 ? pin assignment name pin description osci osco a0 gnd sda scl int vcc 1 2 3 4 5 6 7 8 generator input, 50hz or occurrences generator output address input gnd data for i 2 c - bus clock pulses for i 2 c - bus open - drain interrupt output supply voltage fig.1 ina8583 orderi ng i nform ati on i l 8583n pl asti c i l 8583d soi c t a = - 2 0 ? + 70 c f or al l pac k ages . device operating temperature range package packing il8583n t a = - 20 ? +70c dip - 8 tube IL8583D sop - 8 tube IL8583Dt sop - 8 t&r pinning d i a gram
ina8583 2012, january, ver.01 block d iagram in a 8583 ina8583 osci 100hz 00 osco 01 int v cc gnd 07 08 a0 0f scl ff sda fig. 2. ina 8583 oscillator 32.768khz divider 1:256 or 100:128 control logic power - on reset i 2 c - bus i n terface address register control/status hundredth of a second seconds minutes hours year/date weekday/months timer alarm control alarm regisers or ram ram (2408)
ina8583 2012, january, ver.01 table 2 ? recommend - operating conditions parameter , symbol , unit limits note not more not less supply voltage, vcc, v ? operating ? clock 2.5 1.0 6.0 6.0 t amb = 0 ? +70 c low input voltage, vil, v 0 0.3*vcc high input voltage, vih, v 0.7*vcc vcc operating ambient temper a- ture, tamb, c - 20 +70 input frequency, f i , mhz 1 only for event mode table3 ? absolute maximum rating parameter , symbol , unit limits note not more not less supply voltage, vcc, v - 0.8 7,0 input voltage for all inputs, v i , v - 0.8 vcc+0.8 note1 max output current , io, ma 10 max input current , i i , ma 1 0 current through inputs 04 or 08, i dd , i ss , m : 50 power dissipation on package, j tot , mw 300 3rzhuglvvlsdwlrqrqrxwsxwj h , mw 50 storage temperature , tstg, - 65 +150 notes: 1. if voltage on diode is higher than v cc or lower than gnd, the current will flow, the current should be not more than 0.5ma. * stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the d e- vice. these are stress ratings only and functional operation of the device at these or any other conditions beyond those ind i cated unde r ?recommended operating conditions? is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability.
ina8583 2012, january, ver.01 table 4 ? electrical parameters. parameter, symbol , limit testing co n- ditions temper a- ture, c u nit not less not more supply supply current ,i, a 200 vcc=6v f scl = 100 khz t= - 20 +25 +70 supply current for clock, i 0 , 50 vcc=5v a 10 vcc=1v data storage supply current , i ccr , a 5 note 1 v cc = 1v 2 v cc = 1v i 2 c - bus enable level, v por , v 1.5 2.3 note 2 input /output sda low output current , i ol , ma 3 vcc= 6 v vol= 0.4 v input leakage current, |i i |, a 1 vcc= 6 v v il = 0 v v ih = 6 v scl, sda input capacity, i ,pf 7 v i =0 v inputs a0, osci input leakage current, |i i |, n a 250 vcc= 6 v v il = 0 v v ih = 6 v output int output low current, i ol , ma 3 vcc=6.0 v v ol = 0 ,4 v input leakage current, |i i |, a 1 vcc= 6 v v il = 0 v v ih = 6 v notes: 1. for event mode or 50hz only. 2. the i 2 c - bus logic is disabled if v cc < v por .
ina8583 2012, january, ver.01 description ina8583n contains 2568 ram 8 - bit. th e word address register which is incr e- mented automatically, built - in 32.768 khz oscillator circuit, frequency divider, interface of two line bi - directional s e rial i 2 c - bus and power - on reset circuit. the first 8 bits of the ram (addresses 00 07) are design ated ass addressable 8 - bit parallel registers. the first register (address 00) is used as a control/status register. the memory addresses 01 to 07 are used as counters for the clock function. the memory a d- dress 08 0f may be used as free ram locations or ma y be programmed as alarm regi s- ters. the following modes can be selected by setting the control/status register: ? clock mode from 32.768 khz; ? clock mode from 50 hz; ? event counter mode. in the clock mode hundredths of a second, seconds, minutes, hours, date , month (four - year calendar) and a weekday are stored in a bcd format. the timer register stores up to 99 days. the event counter mode is used for counting pulses applied to the oscill a- tor input (osco left open - circuit). in bcd format the event counter sto res up to 6 digits. by setting the alarm enabling bit of the control/status register the alarm control regi s- ter (address 08) is activated. by setting the alarm control register the following may be programmed: ? dated alarm; ? weekday alarm; ? daily alarm; ? timer alarm. in the clock mode the timer register (address 07) may be programmed to count hu n- dredths of a second, seconds, minutes, hours or days. days are counted when an alarm is not programmed. whenever an alarm event occurs the alarm flag of the control/s tatus register is set, and an overflow condition of the timer will set the timer flag. the open drain interrupt ou t- put is switched on (active low) when the alarm or timer flag is set. the flags remain set until directly reset by a write operation to regist er (00 address). when the alarm is disabled the remaining alarm registers (addresses 09 0f) may be used as free ram. in the clock modes 24hr or 12hr format can be selected by setting the most signif i- cant bit of the hours counter register.
ina8583 2012, january, ver.01 regis ter arrangement control/status control/status 00 hundredth of second d1 d0 01 seconds d3 d2 02 minutes d5 d4 03 hours free 04 year/date free 05 weekday/month free 06 timer timer 1 timer 0 07 alarm control alarm control 08 hundredth of second alarm d1 alarm d0 09 alarm seconds d3 d2 0a alarm minutes d5 d4 0b alarm hours free 0c alarm date free 0d alarm month free 0e alarm timer alarm timer 0f free ram fre e ram clock modes event counter fig . 3 . table 5. ? cycle length of the time counters, clock modes unit counting cycle carry to next unit contents of the month counter hundredths of a second 00 99 99 to 00 seconds 00 59 59 to 00 minutes 00 59 59 to 00 hours (24 h) 00 23 23 to 00 hours (12 h) 12?, 01? 11?, 12, 01 11 11 to 12? date 01 31 01 30 01 29 01 28 31 to 01 30 to 01 29 to 01 28 to 01 1, 3, 5, 7, 8, 10, 12 4, 6, 9, 11 2, year = 0 2, year = 1, 2, 3 months 01 21 12 to 01 year 0 3 3 to 0 weekdays 0 6 6 to 0 timer 00 9 9 no carry
ina8583 2012, january, ver.01 the year and date are packed into memory location 05. the weekdays and months are packed into memory location 06. when reading these memory locations the year and weekdays may be masked out when the mask flag of the control/status register i s set. this allows the user to read the date and month counters only. in the event counter mode data are stored in bcd format. d5 is the most significant and do the least significant digit. in this mode the internal divider is by - passed. by setting the ala rm enable bit of the control/status register the alarm control register (a d- dress 08) is activated. all functions of the alarm, timer and interrupt output are controlled by the contents of the alarm control register. all alarm registers are arranged startin g from 08 address. an alarm signal is generated when the contents of the alarm registers matches bit - by - bit the contents of the involved counter registers. the year and weekday bits are i g- nored in a dated alarm. a daily alarm ignored the month and date bit s. when a weekday alarm is selected, for comparison a bit will be selected from the alarm register per the weekday (address oe) corresponding to the weekday on which the alarm is activated. interrupt output (with open drain) is programmed by setting the a larm control regi s- ter. it enables (active low) when the alarm flag or timer flag are set. the voltage level in on state (high) on the interrupt output may be more than the supply voltage. a 32.768 khz quartz crystal may be connected to osci (pin 1) and os co (pin 2). a tri m mer capacitor between osci and supply is used for tuning the oscillator. a 100 hz clock signal is derived from the quartz oscillator for the clock counters. in the 50hz clock mode or event - counter mode the oscillator is disabled and the o scillator input is switched to a high impedance state. this allows the user to feed the 50hz reference fr e quency or an external high speed event signal into the input osci. when power - up occurs the i 2 c - bus interface, the control/status register and all clo ck counters are reset. after the device starts time - keeping in the 32.768khz clock mode with the 24hr fo r mat on the square wave appears at the interrupt output pin (starts high). this may be abolished by se t ting the alarm enable bit in the control/status r egister. the 2 nd signal of interface of i 2 c - bus is generated as soon as the supply voltage b e low the reset level of i 2 c - bus interface. this reset signal does not affect the registers of hour counter and co n trol/status register. it the recommended to set t he stop counting flag of the control/status register b e- fore loading the actual time into the counters. loading of illegal states may lead to a te m- porary clock malfun c tion. i 2 c - bus is a bi - directional, two - line communication between different ics and mo d- ule s. the two lines are a serial data line (sda) and a serial clock line (scl). both lines shall be connected to a positive supply via a resistor since in ic these outputs have ?open drain?. data transfer may be init i ated only when the bus is not busy.
ina8583 2012, january, ver.01 o ne data bit is transferred during each clock pulse. the data on the sda line must remain stable du r ing the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. . bit transfer sda scl data change valid of data allowed fig. 4. both sda and scl lines remain high when the bus is not busy. the high - to - low tra n sition of the data line, while the clock is high is defined as th e start condition (s). a low - to - high transition of the data line while the clock is high is defined as the stop condition (). definiti on of start and stop conditions sda scl s p fig. 5. a device ge nerating a message is a ?transmitter? a device receiving a message is a ?receiver?. the device that controls the message is the ?master?, and the devices which are co n trolled by the master are ?slaves?. the number of data bytes transferred between the s tart and stop conditions from the transmitter to receiver is unlimited. each byte of eight bits is followed by an acknow l- edge bit.
ina8583 2012, january, ver.01 acknowledgment on the i 2 - bus clock pulse for start condition acknowledgement scl from master 1 2 8 9 data output by receiver data output by transmitter s fig . 6. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave r e- ceiver which is a d dressed must generate an acknowledge after the reception of eac h byte. also a master receiver must generate an acknowledge after the reception o each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse. a master receiver must signal an end of date to the transmitter by not generating an a c knowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. before any date is transmitted on the i 2 c - bus, the device which should respond is addres sed first. the addressing is always carried out with the first byte transmitted after the start proc e dure. master transmits to slave receiver (write) mode acknowledgement acknowledgement acknowledgement from slave from slave from slav e s slave address 0 : word address : data : j r/w n bytes auto increment memory word address fig. 7.
ina8583 2012, january, ver.01 master reads after setting word address (write word address; read data) acknowledgement acknowledgement acknowledgement from slave from slave from slave s slave address 0 word address s slave address 1 r/w r /w at this moment master - transmitter becomes master - receiver and ina8583n slave - receiver becomes slave - transmitter. acknowledgement no acknowledgement from master from master data data 1 n b yte last byte auto increment auto increment word address word address fig. 8. master reads slave immediately after first byte (read mode) acknowledgement acknowledgement no acknowledgement from slave from ma ster from master s slave address 1 data data 1 r/w n bytes last byte auto increment auto increment word address word address fig. 9.
ina8583 2012, january, ver.01 application circuit v cc v cc v cc v cc r r fig.1 0 table 6 ? symbols symbol description s start condition p stop condition a bit acknowledge ina8583 address 1 0 1 0 0 0 0 r/w group1 group 2 fi g. 11. v cc 0 scl osci ina8583 sda osco gnd v cc 0 scl osci ina8583 sda osco gnd master sda transmitter scl
ina8583 2012, january, ver.01 package dimension n suffix plastic dip (ms ? 001ba) symbol min max a 8.51 10.16 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 no tes : l 7.62 8.26 1. dimensions ?a?, ?b? do not include mold flash or protrusions. m 0.2 0.36 maximum mold flash or protrusions 0.25 mm (0.010) per side. n 0.38 d s uffix s oic (ms - 012aa) symbol min max a 4.8 5 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 g h j 0 8 no tes : k 0.1 0.25 1. dimensions a and b do not include mold flash or protrusion. m 0.19 0.25 2. maximum mold flash or protrusion 0.15 mm (0.006) per side p 5.8 6.2 for a; for b ? 0.25 mm (0.010) per s ide. r 0.25 0.5 1.27 5.72 dimens ion, mm dimens ion, mm 2.54 7.62 a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 8 4 5 l h m j a b f g d se ati ng plane n k 0.25 (0.010) m t -t- c 1 8 4 5

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